Digital Logic · 18 November 2026

What Is a Flip-Flop Circuit? SR, D, JK and T Flip-Flops Explained

A flip-flop is one bit of memory made from two gates that feed each other. How the SR latch holds a value, what the clock adds, and what D, JK and T flip-flops are for.

The 60-second version · open on YouTube ↗

A logic gate has no memory. Change its inputs and the output changes; put the inputs back and it forgets anything happened. Yet every computer is built from logic gates, and computers remember things. The trick that makes it possible is one of the oldest ideas in digital electronics: take two gates and feed each one’s output into the other.

What is a flip-flop circuit?

A flip-flop is a circuit that stores one bit. It has two stable states, 0 and 1, and it stays in whichever state it was last put into until something tells it to change. That’s it. Registers, counters, RAM caches, the program counter in a CPU: they’re all rows of flip-flops.

The simplest version is the SR latch (set-reset), and you can build it with two NOR gates.

How does an SR latch remember?

Wire two NOR gates so the output of each one goes to an input of the other. The remaining input on the first gate is S (set); the remaining input on the second is R (reset). Call the outputs Q and Q-bar.

  • Pulse S high: Q goes to 1, Q-bar goes to 0. Release S. Q-bar is 0, which is one of the first gate’s inputs, so the first gate keeps Q at 1. The gates are now holding each other in place.
  • Pulse R high: the mirror image happens. Q goes to 0 and stays there.
  • Both low: nothing changes. This is the “hold” state, and it’s where the memory lives.
  • Both high at the same time: both outputs go to 0, which breaks the rule that Q and Q-bar are opposites. This is the forbidden state. Release both inputs together and the latch lands on whichever gate happens to be a picosecond faster. Unpredictable, so you design around it.

The loop is the memory. Neither gate is doing anything clever; each one is just holding the other in a grip.

What does the clock add?

An SR latch responds the instant S or R changes. In a real system with thousands of these, you want them all to update at the same moment, not whenever their inputs happen to wobble. So you add a clock input and gate S and R through AND gates with it. Now the latch only listens while the clock is high.

Go one step further and make it respond only to the clock’s rising edge, the instant it goes from 0 to 1, and you have a proper flip-flop. The classic way to do that is master-slave: two latches back to back, one that captures while the clock is low and one that passes the value on when the clock goes high. The result is a device that samples its input once per clock tick and ignores it the rest of the time. That’s what lets a CPU run millions of operations in lockstep.

What are the different types of flip-flops for?

They all store one bit. They differ in how you tell them what to store.

D flip-flop (data). One input, D. On the clock edge, Q becomes whatever D was. No forbidden state, because there’s only one input. This is the workhorse: a register is just eight D flip-flops sharing a clock. The 7474 (two per chip) and the CD4013 are the standard parts.

JK flip-flop. Two inputs like SR, but the forbidden state is given a job: J and K both high means toggle. Q flips to the opposite of whatever it was. The name is often credited to Jack Kilby, co-inventor of the integrated circuit, though the story is disputed.

T flip-flop (toggle). One input, T. If T is high on the clock edge, Q flips; if low, it holds. It’s a JK with J and K tied together. Its superpower is that a toggling output runs at exactly half the clock frequency. Chain four of them, each clocked by the previous one’s output, and you’ve built a 4-bit binary counter that counts to 15.

Why do real flip-flops have setup and hold times?

Because the input has to be steady for a few nanoseconds before and after the clock edge. Change D at the exact moment the clock rises and the master latch can be caught half-way between states, a condition called metastability, where Q hovers at a voltage that’s neither 0 nor 1 for an unpredictable time before falling one way or the other. It’s the same ambiguity as the SR forbidden state, and it’s why a noisy button fed straight into a clock input gives you chaos: the bounce lands on edges at random.

Where will I meet one?

Everywhere you need to remember a single thing. A push-on, push-off light switch is a T flip-flop. The “seen” flag on a notification is a D flip-flop. A frequency divider is a chain of them. And the 2 KB of SRAM in an Arduino is sixteen thousand of them, each one two gates holding each other in a grip.

Try it Breadboard an SR latch from one 74HC02 (four NOR gates; you need two). Put an LED on Q, pull-down resistors on S and R, and two buttons to 5 V. Tap S: the LED stays on after you let go. Tap R: it stays off. Press both and release: now you've seen the forbidden state decide for itself.

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Topics: flip flop circuit · flip flop logic circuit · what is flip flop circuit · sr flip flop · d flip flop circuit diagram · jk flip flop · t flip flop · flip flop digital circuit

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